Job description:
Google is conducting an interview for the post of Performance Design Verification Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and aren’t daunted by the challenge of building something from scratch, then our team might be your next career step.
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will solve technical problems with innovative micro-architecture and practical logic solutions.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities:
- Be part of a team to verify complex digital design blocks at Subsystem level or Full Chip level by fully understanding the design specification and interacting with design engineers to identify key verification scenarios.
- Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi core based C tests using reusable C test libs.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Qualifications and Experience required:
- Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with performance verification and experience in gathering/interacting with Architecture and Modeling teams.
- Experience in C/C++ or System Verilog based tests, test sequence development.
- Experience verifying digital logic at the RTL using SystemVerilog.
Preferred qualifications:
- Experience on performance verification of complex SoC with multiple crossbar/networks on chip (NoC’s).
- Experience with debugging performance and latency related issues across multiple subsystems and SoC.
- Experience with QOS, Real time client bandwidth (BW), and other mechanisms of BW control.
- Working knowledge of performance and latency architecture for an ARM-based system on a chip (SoC).
- Working knowledge of performance measurement and debug in an emulation environment.
- Knowledge of performance analysis tools.
Job/Req. ID: N/A
Company: Google
Location: Bengaluru, KA
Job category: Electrical or VLSI Engineering
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