Job description:
Cadence is conducting an interview for the post of Design Engineer II.
Requirements:
- BTech/MTech fresher
- Strong expertise in Verilog, HVL(SV, e) with UVM/OVM/eRM methodology
- Experience in assertions development/closure, constraint randomization, functional coverage, code coverage.
- Strong RTL and GLS debug skills.
Job/Req. ID: R36813
Company: Cadence
Location: Bengaluru, KA
Job Category: VLSI Engineering
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