Job description:
Google is conducting an interview for the post of SoC Design and Electronic Design Automation Methodology Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
You are an experience engineer with Electronic Design Automation (EDA) and design implementation background for our SOC pathfinding program. You will work as part of a cross-functional team to develop state of the art chiplet solutions for consumer applications at Google. In this role, you will perform design analysis holistically across the chiplet partitioning scenarios for SoC, assessing floorplanning, design closure, and PPA analysis.
You have a EDA and design methodologies background, and you will work on the development of effective chiplet integration design methodologies such as physical design, extraction and analysis methodologies, timing and P&R, automation scripts and write documentation, etc. You will perform technical evaluations of EDA vendors, tools, foundry technology nodes, and IPs.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities:
- Research and develop effective heterogeneous integration design methodology and solutions
- Develop and support flows and methodologies for 3DIC/chiplet designs which may include floorplanning, routing, extraction and verification, optimize power, performance, area and cost, thermal, electrical, signal/power integrity and mechanical analysis
- Work with cross functional teams to set requirements and develop effective solutions
- Work with EDA vendors on evaluations, enablement, and debug of advanced or new tools and flows
- Provide documentation, training, and support to product design teams
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Science, Mechanical Engineering, Physics, or related field, or equivalent practical experience
- 5 years of experience in ASIC design, design flows and methodologies, and analysis and simulation tools
- 2 years of experience in IP integration
- Experience in scripting languages such as Python, Tcl, or Perl
Preferred qualifications:
- Experience in 3DIC implementation (such as TSMC CoWoS, InFO technologies, etc.)
- Experience in custom design methodologies
- Experience in die-to-die interface IP evaluation and integration
- Experience in thermal, electrical, SI/PI and/or mechanical analysis
- Experience in power, performance, area and cost optimizations
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: Electrical or Computer Science or mechanical or VLSI Engineering
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