Job description:
Google is conducting an interview for the post of Design Verification Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a part of the Google Silicon Interconnect/Platforms team, you will work on the verification of Google’s SOC offerings. You collaborate with Hardware Architects and Design Engineers for functional and performance verification of the interconnect, cache coherency, and memory consistency. You also closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs.
In this role, you will be verifying a generalized class of interconnects, and developing the associated methodologies and tools needed to solve the problem.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities:
- Plan and execute the verification of configurable interconnects and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or verify designs with SVA and formal tools.
- Develop cross-language tools and scalable verification methodologies.
- Identify and write varying coverage measures for stimulus and corner-cases.
- Debug tests with Design Engineers to deliver functionally correct design blocks.
Qualifications and Experience required:
- Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 2 years of experience verifying digital logic at the RTL-level using SystemVerilog or C/C++.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (i.e. microprocessor cores, hierarchical memory subsystems).
Preferred qualifications:
- Master’s or PhD degree in Electrical Engineering or Computer Science.
- Experience in one or more of the following: Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, and/or Packet Processors.
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
- Experience with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
- Experience building verification methodologies that span simulation, emulation, and FPGA prototypes.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: Electrical or VLSI Engineering
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