Job description:
Google is conducting an interview for the post of Physical Design Methodology Engineer, ASIC.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Physical Design Methodology Engineer, you will be developing high-performance and low-power hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC).
You will work with the Implementation Engineers to understand the PPA (power, performance, and area) and schedule goals and concerns. You will also drive optimizations through custom solutions or through engagement with the EDA that will continuously improve the PPA and make the execution more efficient.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities:
Drive PPA (power, performance, and area) optimizations within a tight delivery schedule.
Work closely with the block owners to enable quick assimilations of optimizations.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Technology, or related field or equivalent practical experience.
- Experience scripting in Tcl, Perl, or Shell.
- Experience in one or more of synthesis or PnR tools (e.g., Genus, Innovus, DC and ICC, STA tools).
- Experience in high-performance synthesis, PnR, and sign-off optimizations, and PPA optimization delivery.
Preferred qualifications:
- Experience in AI-based optimizations.
- Understanding of the fundamentals of computer architecture.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: VLSI or Electrical Engineering
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