Job description:
Synopsys is conducting an interview for Engineers.
Requirements:
- ME or BE (Electrical or Electronics) with 0-1 years of experience in logic design and implementation using FPGAs
- Strong knowledge of Digital design and FPGA Timing Concepts
- Strong knowledge of Verification concepts, writing test benches and RTL/Netlist simulation.
- Very good hands-on experience in Verilog and/or VHDL.
- Strong in problem solving skills.
- Should have good experience in Synthesis, back-end flow, FPGA architecture and implementing designs in hardware.
- Excellent communication and inter-personal skills, professional attitude, and strong desire to succeed.
- Scripting knowledge is desirable.
- Exposure to Xilinx/Altera synthesis software is a plus.
- Ability of Multitasking is a Plus
Job/Req. ID: 37667BR
Company: Synopsys
Location: Bangalore, KA
Job Category: VLSI or Electronics or Electrical Engineering
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