Job description:
Synopsys is seeking a motivated and innovative digital verification engineer with excellent theoretical and practical background in high-speed data recovery circuits. Candidate will be involved in verifying current and next generation SERDES products.
Job duties and responsibilities:
- Writing constrained-random System Verilog test benches using UVM and VMM.
- Writing new cover group and examine functional, assertions and code coverage.
- Defining and tracking verification test plans;
- Debugging RTL and gate-level simulations failures;
Requirements:
- Bachelor’s or Masters Degree in ECE/EEE
- Candidates should have experience writing scripts in languages such as Perl, Python, Unix shell.
Job/Req. ID: 39557BR
Company: Synopsys
Location: Hyderabad, Telangana
Job Category: VLSI or ECE or EEE Engineering
Join all India VLSI Jobs Telegram Group
Sorry, the job you’re looking for is not available. There are other latest opportunities you might be interested in. Check them out on the homepage.
