ASIC/Layout Design Engineer, I (39902BR) | Synopsys | Hyderabad, Telangana

Job description:

Synopsys is conducting an interview for the post of ASIC/Layout Design Engineer.


  • Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, Clock cells other complex circuits.
  • Strong Knowledge and Hands-on experience in developing environment and extraction of post layout netlist Good understanding of CMOS device characteristics, design rules, Latch Up, Electromigration.
  • Good understanding of Digital circuits and optimization for better PPA.
  • Decent knowledge of Python/Shell/ICV coding will be preferable.
  • Having Good understanding of std cell Layout is a plus.
  • Good verbal and written communication skills.

Job/Req. ID: 39902BR

Company: Synopsys

Location: Hyderabad, Telangana

Job Category: VLSI Engineering

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