Job description:
Intel is conducting an interview for the post of IO Layout Design Engineer.
Job duties and responsibilities:
As a member of the Advanced Design Library technology group in TMG/DE, you will be at the vanguard of designing analog foundational IP on leading edge Intel processes to meet density and performance scaling goals of Intel CPU and SoC products. AD serves as the design interface with the process development team, working out key design/process interactions for all new processes. You will be responsible for design, Silicon validation and support of primitive copy-exact analog foundational IP that relate to Electrostatic Discharge (ESD) protection device design and integration. These IPs include: ESD diodes, Power clamps, analog transistors, resistors, capacitors, thermal sensing devices and others.
Responsibilities include but not limited to:
- Define copy-exact foundational IP in collaboration with analog and I/O designers in product groups and AD.
- Work with process/device/Reliability stake holders as part of DTCO to co-optimize design and process modeling/rules.
- Validate and implement through characterization flows.
- Develop and support scripts/automation for supporting any technology specific layout changes.
- Ensure industry standard TFM and EDA support is enabled for all collaterals.
- Work with respective stakeholders and efficiently communicate across team and geographies.
Minimum Qualification:
- Candidate should possess a master’s in degree in Electrical Engineering Electronics Engineering.
- Minimum 1 year experience in scripting/coding in SKILL/Python or any scripting language.
- Solid understanding of semiconductor device physics.
- Experience in layout design of critical ESD circuits, Custom and ASIC Physical Design, RV.
- Knowledge of Electronic Design Automation tools, flows and methodology like Virtuoso XL.
- Understand Layout cleanup expertise and ability to perform DRCs, LVS verifications.
- Strong analytical ability, problem solving and communication skills.
Preferred Qualifications:
- Minimum 2 years of experience with strong VLSI design knowledge, circuit design knowledge and layout/template development.
- Minimum 2 years in layout automation and scripting and coding for automation in SKILL/Python or other programing languages.
- Experience in Custom, Analog Layout, Mixed Signal layout design.
- Background in semiconductor behavior under ESD conditions.
Job/Req. ID: JR0232469
Company: Intel
Location: Bangalore, KA
Job Category: VLSI or Electrical or Electronics Engineering
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