ASIC Design for Testability Engineer | Google | Bangalore, KA

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Job description:

Google is conducting an interview for the post of ASIC Design for Testability Engineer.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • Experience with ATPG, LV, BIST, JTAG tools and flow.
  • Experience in DFT of IPs (e.g., CPU, GPU, DDR).

Preferred qualifications:

  • Knowledge of high performance design DFT techniques.
  • Ability to scale DFT, with a focus on minimal area overhead.
  • Understanding of the end to end flows of Design, Verification, DFT, and PD.
  • Proficient with a scripting language such as Perl.
  • Proficient with Synthesis, Lint, CDC, LEC and DFT timing and STA.

Job/Req. ID: N/A

Company: Google

LocationBangalore, KA

Job CategoryVLSI Engineering

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