Job description:
ARM is conducting an interview for the post of Design Engineer.
About the team:
- We are the POP Implementation team which is part of Physical Design Group(PDG) at Arm.
- POP team is an experience to see the bigger picture of technical, business and problem solving aspects through the journey of building Arm CPU, GPU, NPU and Interconnect implementations. So what are the aspects we touch upon a daily basis?
- We do the physical implementation of Arm’s latest CPU, GPU, NPU and Interconnect IP!
- We have exposure to advanced and mainstream technology nodes(3nm/5nm/7nm/12nm/22nm) across multiple foundries!
- We indulge in path-finding of Performance, Power and Area(PPA) metrics using optimized recipes along with backend closure that’s representative of a tape-out.
- We develop physical implementation flows and exercise PPA tuning across multiple vendor based EDA flows(Cadence/Synopsys) in parallel.
- We work closely with Arm sales, marketing and end customers to refine the physical IP and implementation products.
- Contribute in brainstorming ideas, approaches and recipes on all products being crafted in the team.
- Learn the intricacies of supporting products across different market segments like Client, Infrastructure, Automotive, IOT and Machine Learning.
- Celebrate the product and customer success with the whole team for accomplishing greater things in future.
Job duties and responsibilities:
- You will be encouraged to build implementations of Arm CPU/GPU class designs using PDG’s optimized physical IP.
- The process involves RTL setup, integration of memory models, creation of floorplans and finding the rewarding recipe of synthesis / P&R flow.
- The primary objective would be to optimize performance, power and area as required by the Arm IP and the associated market segment.
- In terms of backend closure, you will need to take the design through STA, EM, IR drop, signoff DRC and other types of verification steps.
- There are lighter aspects related to DFT(scan insertion, compression and ATPG) and Gate-level simulations to report power.
- Your daily job will demand a lot of handshaking with physical IP teams who are responsible for “optimized” standard cell and memories.
- There is a need to engage with EDA partners in an independent manner to create and deploy recipes related to EDA tools.
- You will see exposure to commercial teams at Arm. This will extend to end customers also as you evolve over time.
- Interacting with end customers directly to help them in usage of POP IP through the complete customer product tape-out cycle.
- Encouraged to drive experiential learning sessions with wider audiences.
Qualifications and Experience required:
- Bachelors/Masters with 4-12 years of minimum experience in Physical Design domain.
- Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies.
- Strong understanding in the RTL2GDSII flow for leading or mainstream process technologies.
- Good understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure.
- Any implementation experience on Arm CPU and GPU IP designs would be excellent.
- Expertise on optimizing for cost functions like performance, power and/or area is like gold dust.
- High-level know-how related to foundation IPs like standard cells and memories fits well with our work.
- Working experience with tools like DC/Genus, ICC2/Innovus, Primetime/Tempus and others relevant for physical implementation.
- Good automation skills in PERL, TCL and EDA tool specific scripting can be impactful.
Job/Req. ID: 2022-7165
Company: ARM
Location: Bangalore, KA
Job Category: VLSI Engineering
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