Synopsys is conducting an internship for Engineers.
Qualifications and other requirements:
- Good analog circuit analysis and debugging, CMOS fundamentals
- Debugging RTL and gate-level simulation failures
- Candidates should have experience writing scripts in languages such as Perl and Python.
- Good understanding with Verilog and SystemVerilog
- Familiarity with VMM/UVM can be preferred
Job/Req. ID: 43567BR
Job Category: VLSI Engineering
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