Formal Design Verification Engineer, Machine Learning | Google | Bangalore, KA

Job description:

Google is conducting an interview for the post of Silicon Design Verification Engineer.

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

As a Design Verification Engineer, you will be part of a Research and Development team developing hardware and software to enable Google’s continuous innovations. You will be responsible for building verification components, constrained-random testing, end-to-end system testing, and verification closure.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Job duties and responsibilities:

  • Create formal verification test plans and implement formal models and properties to verify complex digital design blocks, collaborate with the design team to analyze and improve design specifications.
  • Utilize formal model checking tools combined with formal closure techniques to achieve formal verification sign-offs.
  • Architect and implement reusable formal verification components.
  • Drive improvements to methodologies and flows to improve formal verification quality and efficiency.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 3 years of experience with SystemVerilog and SystemVerilog Assertion.
  • Experience with formal verification.

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering, Computer Science, or a related field.
  • Experience with verification of AI accelerator, CPU, GPU or other large ASIC systems.
  • Experience with scripting languages, such as Python/Perl and TCL.
  • Experience with formal sign-offs of industry ASIC designs.
  • Knowledge of formal verification applications such as datapath verification, equivalence checking, and connectivity checking.
  • Understanding of formal methodology and formal abstraction techniques.

Job/Req. ID: N/A

Company: Google

LocationBangalore, KA

Job CategoryVLSI Engineering

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