Job description:
Intel is conducting an interview for the post of Physical Design Engineer.
Job duties and responsibilities:
- Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts Block level floor plans abstract view generation
- RC extraction and schematic layout verification and debug using phases of physical design development including parasitic extraction clock generation custom polygon editing auto place and route algorithms floor planning full chip assembly
- RV DFM Density and verification
- Troubleshoots design issues and applies proactive intervention
- May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments
Qualifications required:
You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing Experience.
Skills:
- Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs
- Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks in to the FC floorplan
- Ability to comprehend issues of RC delay electromigration self heating and cross capacitance
- Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout
Inside this business group:
The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel’s leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.
Job/Req. ID: JR0243284
Company: Intel
Location: Bangalore, KA
Job Category: VLSI Engineering
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