Job description:
UST is conducting an interview for the post of VLSI Associate I.
Job duties and responsibilities:
Works under supervision and guidance to execute internal tasks in any field of VLSI Frontend Backend or Analog design
Outcomes:
- Works as an individual contributor and on any one task of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
- Complete the assigned task in the defined domain(s) successfully and on-time with support from other team members and senior engineers
- Ensure quality delivery as approved by the senior engineer
Measures of Outcomes:
- Quality – verified using relevant metrics by Lead
- Timely delivery – verified using relevant metrics by Lead
- Reduction in cycle time and cost using innovative approaches
- Number of trainings attended
Technical skills:
Build up required technical skills and design knowledge to execute the assigned tasks
Quality of the deliverables:
- Clean delivery of the module in-terms of ease in integration at the top level
- Meeting functional spec / design guidelines at least 80% of the time without deviation or limitation
- Documentation of tasks and work performed
Timely delivery:
- Meeting project timelines as set forth by the team lead
- Help with intermediate tasks delivery with other team members to aid progress
Teamwork:
- Participation in teamwork at the time of need
- Able to take on additional tasks incase of any team member(s) is not available
Innovation & creativity:
- Understand how to approach repetitive work by automating tasks saving design cycle time
- Participation in technical discussion
- training
- forum
Role proficiency:
Works under supervision and guidance to execute internal tasks in any field of VLSI Frontend Backend or Analog design Outcomes: Works as an individual contributor and on any one task of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Complete the assigned task in the defined domain(s) successfully and on-time with support from other team members and senior engineers Ensure quality delivery as approved by the senior engineer
Measures of Outcomes: Quality –verified using relevant metrics by Lead Timely delivery – verified using relevant metrics by Lead Reduction in cycle time and cost using innovative approaches Number of trainings attended
Technical Skills: Build up required technical skills and design knowledge to execute the assigned tasks
Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top level Meeting functional spec / design guidelines at least 80% of the time without deviation or limitation Documentation of tasks and work performed
Timely delivery: Meeting project timelines as set forth by the team lead Help with intermediate tasks delivery with other team members to aid progress
Teamwork: Participation in teamwork at the time of need Able to take on additional tasks incase of any team member(s) is not available
Innovation & Creativity: Understand how to approach repetitive work by automating tasks saving design cycle time Participation in technical discussion training forum
Skill Examples: Languages and Programming skills: System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
EDA Tools:
- Cadence Synopsys Mentor tool sets (one or more)
- Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
Technical Knowledge: (any one)
- Learn to understand IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verification
- Theoretical knowledge in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecture
- Fair knowledge of Physical Design / Circuit Design / Analog Layout
- Fair understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verification Technology: CMOS FinFet FDSOI – 28nm / 22nm / 16ff / 10nm and below
- Able to deliver the tasks with quality at least 80 % on-time per quality guidelines and GANTT
- Good communication skills
- Good analytical reasoning and problem-solving skills and attention to details
- Ability to learn new skills in case required technical skills are not present at a level needed to execute the project
Skill examples:
Languages and Programming skills: System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
Technical Knowledge: (any one)
- Learn to understand IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verification
- Theoretical knowledge in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecture
- Fair knowledge of Physical Design / Circuit Design / Analog Layout
- Fair understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verification
Technology:
- CMOS FinFet FDSOI – 28nm / 22nm / 16ff / 10nm and below
- Able to deliver the tasks with quality at least 80 % on-time per quality guidelines and GANTT
- Good communication skills
- Good analytical reasoning and problem-solving skills and attention to details
- Ability to learn new skills in case required technical skills are not present at a level needed to execute the project
Knowledge examples:
- Basic understanding in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
- Understanding of the design flow and methodologies used in the designing
- Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the manager per skill set
Job/Req. ID: 99123359
Company: UST
Location: Bangalore, KA
Job Category: VLSI Engineering
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