Job description:
Google India is conducting an interview for the post of Physical Design Engineer.
Job duties and responsibilities:
- Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
- Manage block and full-chip level physical implementation and QoR (e.g., power, timing, area).
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience in physical design implementation.
- Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
- Experience in high performance synthesis, PnR and sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks, and physical verification.
Preferred qualifications:
- Knowledge of STA and sign-off convergence methodology.
- Knowledge of industry standard implementation tools.
- Fundamentals of computer architecture and Knowledge of Verilog/SystemVerilog.
- Understanding of Circuit design, device physics, and deep submicron technology.
- Excellent scripting skills in scripting languages (e.g., Python, Tcl, and/or Perl).
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job category: Electrical or VLSI Engineering
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