Google is hiring ASIC RTL Design Engineers.
Job duties and responsibilities:
- Interact closely with the Architecture team and develop microarchitecture and coding to meet quality and Performance Power Area (PPA) for the IP.
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and silicon bring-up.
- Participate in test plan and coverage analysis of the IP, sub-system, and chip-level verification.
- Work with multi-disciplined and multi-site teams in RTL design, verification, DFT, physical design, software team, architects.
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- Experience in design and multi-power domains with clocking.
- Experience in coding using Verilog or System Verilog.
- Master’s degree in Electrical Engineering, or a related field.
- 4 years of experience in RTL coding from domains such as interconnect, coherency/non-coherency, or cache.
- Proficiency with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, UPF, and Low Power Optimization/Estimation.
- Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
Job/Req. ID: N/A
Location: Bangalore, KA
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