MTS Silicon Design Engineer (Front End Physical Design) | AMD Job | Hyderabad, Telangana

December 30, 2023

Job description:

AMD is conducting an interview for the post of MTS Silicon Design Engineer.

Job duties and responsibilities:

The focus of this role is to be responsible for GFXIP Front-End implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.

The person:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key responsibilities:

Responsible for GFXIP Front-End implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
Responsible for block and tile level synthesis, timing analysis and optimization, equivalence check
Responsible for functional ECO implementation
Responsible for block design quality check, including Lint, CDC, DFT
Responsible for Front End design methodology and flow development
Build the directed and random verification tests
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Preferred experience:

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment.
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Good working knowledge of SystemC and TLM with some related experience.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
Exposure to leadership or mentorship is an asset
Desirable assets with prior exposure to video codec system or other multimedia solutions.