Standard Cell Design Engineer | Micron Technology Job | Hyderabad, Telangana

February 13, 2024

Job description:

Micron Technology is hiring for the post of Standard Cell Design Engineer.

Job duties and responsibilities:

As a Scalable Standard cell Design Engineer at Micron technology Inc., Engineer you will work in a highly innovative, motivated, Upbeat, and motivated design team using pioneering memory technologies to develop the most advanced DRAM technology and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips with huge scale of circuit capability, ultra-high-speed designs, intricate functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and low power and power management technologies. You will need to have the ability to work as a Memory Analog and Stdcell Characterization Validation Engineer, to verify and validate the Analog block circuitry and standard cells through the verification methodology and tools. You will work closely with Micron’s various design and verification teams all over the world to chip in to the success of the design projects by applying verification tools and techniques, providing verification status and summaries to specific designs as needed.

Essential responsibilities:

Design and maintain standard cells for new products based on new technology.
Characterize the performance of standard cells and optimize the standard cell design and layout.
Characterization and modeling of Standard Cell and specific Custom cells to provide timing/power model for verification.
Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality.
Develop automation test bench/flow/tools to improve the work efficiency and help data analysis.
Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
Participate in developing verification methodology and verification environments for DRAM technology and emerging memory products.

Qualifications and experience required:

Bachelor’s or Post Graduate Degree in Electronics Engineering or related engineering field with 0-2 years Relevant experience required.

Skills required:

Good understanding of CMOS circuit design
Good knowledge of CMOS device physics and layout
Experience in Siliconsmart, Liberate, Liberate_LV, Primetime, Solido Analytics and Cadence Virtuoso preferred.
Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision
Experience in Analog block design and verification preferred.
Experience in Standard Cell design and verification
Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis is a plus
Previous work experience in DRAM memory related fields is a plus.
Must possess good interpersonal & communication skills and ability to work well in a team