Job description:
Google is hiring for the post of RTL Design Engineer.
About the team:
Your team designs and builds the hardware, software and networking technologies that power all of Google’s services.
Job duties and responsibilities:
As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
- Define the block level design document (i.e., interface protocol, block diagram, transaction flow, pipelines, etc.),
- Perform RTL development (i.e. coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SoC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience with ARM-based SoCs, interconnects and ASIC methodology
Preferred qualifications:
- Master’s degree in Electrical/Computer Engineering
- 3 years of experience with IP design for clocking, interconnects, peripherals
- Experience with methodologies for low power estimation, timing closure, synthesis
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: VLSI or Electrical or Computer Engineering
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