IP Front-End and Verification M/F | STMicroelectronics | Noida, UP

Job description:

STMicroelectronics is conducting an interview for the post of IP Front-End and Verification M/F.

Job duties and responsibilities:

  • Involved in Front-End IP Design and Verification flow related to Memory IPs, AMS and Analog block behavioral models. Required to develop First-time right, functionally accurate and robust behavioral models and other Front-end views along with intent of striving for zero defects.
  • Role involves developing Model architecture and Specs, module architecture, coding using Verilog and System Verilog. Also required good know-how of DFT Flow, Block level designer verifications, Front-end implementation tasks, Lint/CDC checks, Synthesis flow. Working with DV team, review test-plans for DV signoff.


  • Competence to Develop (from Specs definition to Behavior Model, and Timing annotation and checkers), with continuous focus on innovation and achievement of end goal.
  • Good knowledge of Memory IPs (Single/Multi Port SRAM, ROM, etc), Analog IPs (ADC, DAC, PLL, Regulators, Oscillators, etc.).
  • Proficiency in HDL languages Verilog/SV languages.
  • Good understanding of Digital VLSI Design Flow (RTL, Simulations, Synthesis, STA, DFT).
  • Should have good knowledge of Tcl and Perl scripting.

Other Good to have skills:

Adaptable, Flexible, Global Approach, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

Solutions orientation; Quality driven; Execution minded; Customer focused;

Candidate criteria:

Education level required:

4 – Bachelor degree

Experience level required:

2-5 years


  • English (2- Business fluent)
  • Hindi (1- Basic)

Job/Req. ID: 2021-17614

Company: STMicroelectronics

LocationNoida, UP

Job Category: VLSI Engineering

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