ASIC/Layout Design Engineer (34054BR) | Synopsys | Noida, UP

Job description:

Synopsys is conducting an interview for the post of ASIC/Layout Design Engineer.

Job duties and responsibilities:

You will be part of an rapidly growing development team in the area of GPIOs , Specialty IOs and General Purpose Analog IPs

  • You will develop layouts designs for Analog Full Custom IPs such as
    • GPIOs , I2C, I3C , SMBUS , eMMC , SVID , Quad SPI , JTAG
    • High performance LVDS
    • Crystal Oscillators
    • Adaptive Bias Generator , Process Monitoring Block, Voltage Regulators
  • You will be working with experienced set of teams from various sites spread across globe.

Technical attributes:

  • Good grip over CMOS circuit layout fundamentals, Technology effects, IO frame design methodology, Analog matching concepts
  • Should have good understanding of layout and parasitic extraction.
  • Should have good grip over automation /scripting languages

Personal attributes:

  • Has a dedicated desire to learn and explore new technologies.
  • Demonstrates good analysis and problem-solving skills.
  • High energy person with the ability to go an extra mile.
  • A proactive team player with good written and verbal communication skills.
  • Networks with senior internal and external personnel in own area of understanding.

Job/Req. ID: 34054BR


LocationNoida, UP

Job CategoryVLSI Engineering

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