Job description:
Synopsys is conducting an internship for Engineers.
Job duties and responsibilities:
Responsible for developing backend ASIC design flow from netlist to gdsii & Physical verification for validating the std cell libraries . Also need to work on automation using perl and tcl for enhancing the design flow.
Qualifications and Experience required:
- Bachelors or Masters degree in electronics or electrical engineering (B. Tech/M. Tech) or equivalent from reputed universities.
- Knowledge on VLSI technology
- Gate level and circuit level understanding of CMOS logic design.
- Experience in physical design implementation flow (floorplan, placement, CTS and routing)
- Scripting in Perl and TCL
- Understanding of timing and design closure aspects
- DRC/LVS understanding
- Good communication, interpersonal skills and team player
Job/Req. ID: 34373BR
Company: Synopsys
Location: Bengaluru, KA
Job Category: Electronics or Electrical Engineering
Join all India Electronics Jobs or Electrical Jobs or VLSI Jobs Telegram Group
Join all India Electronics Jobs or Electrical Jobs WhatsApp Group
Sorry, the job you’re looking for is not available. There are other latest opportunities you might be interested in. Check them out on the homepage.
