Synopsys is seeking a motivated and innovative digital verification engineer with excellent theoretical and practical background in high-speed data recovery circuits. Candidate will be involved in verifying current and next generation SERDES products.
Job duties and responsibilities:
- Writing constrained-random System Verilog test benches using UVM and VMM.
- Writing new cover group and examine functional, assertions and code coverage.
- Defining and tracking verification test plans;
- Debugging RTL and gate-level simulations failures;
Qualifications and other requirements:
- Bachelor’s or Masters Degree in ECE/EEE
- Candidates should have experience writing scripts in languages such as Perl, Python, Unix shell.
Job/Req. ID: 34624BR
Location: Hyderabad, Telangana
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