Intern – Frontend RTL and DFT Engineer | GlobalFoundries | Bangalore, KA

Job description:

GlobalFoundries is conducting an internship for Engineers.

Essential Responsibilities:

• As a RTL and DFT Engineer in the team, you will be working independently on RTL Architecture, Implementation, DFT methodologies and post Silicon Debug / Analysis for the high speed mixed signal designs. Being automotive would require field test, BIST and advanced fault models to meet the test goals and quality. You will be responsible for resolving challenges for digital as well as analog DFT to bring down test time and test cost for the product. Expected to interact with the global product and test engineering teams.Experience with owning chip level DFT architecture, execution and Post Silicon debug / analysis
• RTL Design and integration for System on Chip (SOC) from initial specification till tapeout and beyond.
• Fluency in coding RTL in system Verilog and doing validation in tools like Cadence Verilog XL, NCSim, Cadence Simvision, Cadence XCelium, Synopsis Verdi, Synopsis VCSMX, Cadence Genus, Synopsis DC.
• Documenting the SOC design and micro-architecture for usage by other SOC functions
  Specific Knowledge/Skills
• Familiarity with Computer architecture: knowledge of microprocessors, bus protocols preferred.
• Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.
• Experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation.
• Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc)

Qualifications required:

• Requires a ME/MS/MTECH in VLSI, Microelectronics from an accredited university.

Job/Req. ID: 22002734