Job description:
Cadence is conducting an interview for the post of Design Engineering Architect.
Job requirements:
- Complete understanding of power sensitive elements in typical rack based system, from silicon to surrounding firmware that enables power savings
- Ability to analyze performance bottlenecks at a chip or system level
- Influence rtl changes that help act as debug tools while chip is in functional or diagnostic use
- Review IP / rtl / verification plans and influence methodology
- Sound knowledge of asic development flow including understanding of tools / methodologies that are focused on providing power – performance tradeoff.
- Ability to profile the power of a given system and analyze the various contributors and be able to create knobs that can mimic academic and real life profiles
- Ability to work with RTL/verif/Physical design / validation engineers to corelate actual power numbers with various forms of simulations. Should be comfortable going through Verilog/system Verilog code that is associated with power sensitive behavior
- Good understanding of High speed IO [ DDR / serdes ] used in standard SOCs and associated configuration options that change power profiles
- Good understanding of asic validation process
- Hands on abilities to use tune various tools that help in doing power profiling in a custom environment. Will require familiarity with shell / python scripting / C / C ++
Job/Req. ID: R35003
Company: Cadence
Location: Bangalore, KA
Job Category: VLSI Engineering
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