Job description:
Texas Instruments is conducting an interview for the post of Layout Engineer.
Job duties and responsibilities:
- Layout of a block/device, this includes but not limited to schedule, planning, tracking and communicating the layout milestones, floorplan, power-plan, constraint management, layout, verification, extraction, drive and attend reviews, interface with assembly team for package requirements, interface with the fab, for tapeout/PG,
- Develop individual block layout specification based on top level layout requirements.
- Guide the design team on layout DFM constraints like matching, parasitics, EM, ESD, Latch-up, WPE, LoD etc.
- Aggressively drive area reduction, maximize re-use
- Aggressively drive productivity improvement initiatives through automation, flow-methodologies improvements, checklists etc.
- Push the envelope on fab. process capabilities by working with process team for waivers, customizing verification rule decks and/or process flavors
- Push the envelope on assembly capabilities by working with packing team for new package development, optimize layout to fit in to multiple packages
- Write custom verification checks to enhance quality and/or reduce verification turn-around time
Requirements:
B.Tech/M.Tech
Job/Req. ID: 220001YI
Company: Texas Instruments
Location: Bangalore, KA
Job Category: VLSI Engineering
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