GlobalFoundries is hiring for the post of Layout Intern.
This position is for a Layout Engineer who will work on Layout related topics. The successful candidate needs to have a good understanding of CMOS & RF technology and working experience in FinFet and CMOS technologies.
Job duties and responsibilities:
- Work closely with the design team to provide high quality layout in a timely manner
- Work on block level, macro level and top level; floor planning, assembly and verification
- Requires a Bachelor of Engineering B.E./B.Tech or equivalent degree in a related field from an accredited university.
- Strong familiarity with Cadence Virtuoso, Layout XL, Calibre and Unix
- Knowledge of layout techniques for device matching, parasitic reduction, RF shielding, optimal high frequency routing
- Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
- Knowledge of advanced process challenges, including ESD and Reliability
- Exposure to all, or parts of the entire design stack – device physics, fabrication technology, circuit design, standard cells, memory/hard macros, SOC integration
- Language Fluency – Fluent in English Language – written & verbal.
- Must have proficient knowledge of and experience with Unix environment
- Must have hands-on experience with SKILL language
- Should be fluent with Cadence EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking)
- Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
- Be able to collaborate with program and technical design leads on multiple concurrent projects.
- Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
- Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process
- Good understanding of CMOS, FinFet & RF technology
Job/Req. ID: JR-2300196
Location: Bangalore, KA
Job Category: VLSI Engineering
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