DV Engineer Job Opportunity | Microsoft | Bangalore, KA

Analysis and Design of Analog Integrated Circuits Book for your reference

Job description:

Microsoft is conducting an interview for the post of Digital Verification Engineer.

Job duties and responsibilities:

As part of the verification team, you will be responsible for independently creating leading edge constrained-random verification environments and using them to drive functional correctness of innovative designs.

Qualifications and experience required:

  • BS and/or MS in Electrical Engineering or equivalent degree
  • 2+ years of experience in ASIC/SoC verification with SV/UVM environments
  • In-depth knowledge of verification flows and debug strategy
  • Understanding of constrained random verification process, functional coverage, assertion methodology & philosophy
  • Excellent communication skills and the desire to take on diverse challenges
  • Ability to code and debug in C/C++, Python, Ruby or other scripting languages
  • Knowledge of Computer & SoC architecture/design

Job/Req. ID: 1530249

Company: Microsoft

Location: Bangalore, KA

Job Category: Electrical or VLSI Engineering

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