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Job description:
NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs.
This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
Job duties and responsibilities:
In this position, you will expected to lead all block/chip level PD activities.
- PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
- Help team members in debugging tool/design related issues.
- Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
- Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
Qualifications and experience required:
- BE/BTECH/MTECH, or equivalent experience.
- 2+ years of experience in Physical Design.
- Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
- Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
- Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
- Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
- Ability to multi-task and flexibility to work in global environment.
- Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.
Job/Req. ID: JR1965715
Company: NVIDIA
Location: Bangalore and Hyderabad
Job Category: VLSI Engineering
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