Memory Layout Engineer | Texas Instruments | Bangalore, KA

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Job description:

Texas Instruments is conducting an interview for the post of Memory Layout Engineer.

About the team and work:

TI’s ATD memory team is responsible for developing very low power, low cost and high performance single and multiport SRAM, ROM and other Memory IP for technology nodes ranging from 130nm to 28nm. This team has the charter to define, develop and support different memories required to support various TI business units. In this critical role, you will get an opportunity to directly impact our products with best-in-class industry competitive compilers.

Job duties and responsibilities:

  • As a Compiler Memory Layout Engineer in the team, you will be responsible for working independently on layout development of low power, low cost, high performance memory designs.
  • Work with Memory designer to understand the requirements, design and architecture of the compiler memory.
  • Layout development and verification of leaf cells of bitcell, sense amplifier, write driver, power switch, retention diode, row driver, control block etc.
  • Full Instance generation and LVS, DRC, Antenna, EMIR QC checks of layouts.
  • Good knowledge of skill, perl and shell programming to be able to automate repeatable tasks for productivity improvements in layout.
  • Understanding and driving methodology improvements in layout for productivity improvement.
  • Analyze and drive systematic improvements based on lessons learned from Silicon failures.

Qualifications and experience required:

  • Experienced with Memory layout and full development cycle in multiple technology nodes.
  • Proficient in memory layout techniques and pre-silicon verification.
  • Effective communication skills to interact with all team members and stakeholders.
  • Must be highly focused and remain committed to obtaining closure on project goals.
  • Good interpersonal skills to be able to work and collaborate effectively with other team members and stakeholders.
  • Must have good mentoring skills to mentor and guide junior team members in the team.

Preferred skills/experience:

1-3 years of experience in Memory Layout Development.

Job/Req. ID: N/A

Company: Texas Instruments

Location: Bangalore, KA

Job Category: VLSI Engineering

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