SoC Low Power Design Engineer | Google | Bangalore, KA

Job description:

Google is conducting an interview for the post of SoC Low Power Design Engineer.

Job duties and responsibilities:

  • Work with architecture/microarchitecture, architecture/RTL design teams on capturing power intent and convergence.
  • Review the front end low power static checks and drive UPF and VCLP convergence and Sign-off.
  • Support RTL and DFT teams on the Unified Power Format (UPF) aspect in incorporating Physical Design team feedback.
  • Manage cross domains such as DFT, DV and RTL in addressing any UPF/Power intent related methodology and issues.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience in structural power implementation and checks using power-aware flows.
  • Experience in UPF power intent, UPF methodology, and downstream usage in DV and Physical Design tools and flows.

Preferred qualifications:

  • Experience in UPF development of IP, sub-system, or SoC.
  • Experience with low power design techniques and methodologies.
  • Experience with scripting languages (e.g., Python, Perl).
  • Experience in low power static check tools such as VCLP/CLP across RTL to PNR level.
  • Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking and power management.

Job/Req. ID: N/A

Company: Google

LocationBangalore, KA

Job category: Electrical or VLSI Engineering

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