Job description:
Google is conducting an interview for the post of ASIC Electrical Analysis and Convergence Engineer.
Job duties and responsibilities:
- Be the end-to-end owner of EMIR closure for one or more physical design partitions or top level.
- Optimize and drive power, performance, and area based on IP needs.
Minimum qualifications:
- Bachelor’s degree in Electrical, Electronics Engineering, or equivalent practical experience.
- 2 years of experience in die side PDN sign-off.
- Tool experience in RedHawk or Voltus, and experience debugging EMIR issues.
Preferred qualifications:
- Expertise in PPA critical IP PDN convergence in advanced tech nodes.
- Ability to drive PDN (i.e. IR and EM) convergence of multiple low to mid-complexity IPs in terms of Grid Robustness, Static IR, Dynamic IR, Power EM, Signal EM.
- Ability to write low-moderate complexity codes/scripts to simplify debugging and speed up convergence.
- Ability to suggest low-moderate complexity flow improvements and work with CAD to improve the flow.
- Ability to drive PG bump assignment for IPs.
- Ability to manage extended workforce and guide junior level engineers and interns to drive convergence of multiple IP’s or methodology initiatives.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job category: Electrical or Electronics or VLSI Engineering
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