DFT Design Verification Engineer, Test Infrastructure | Google Job | Bangalore, KA

February 17, 2024

Job description:

Google is hiring for the post of DFT Design Verification Engineer.

Google’s computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will work closely with various teams within the design process with other engineers to deliver the design of the chip. You will collaborate with the Functional Verification team to develop Design for Testing (DFT) verification environments, drive DFT verification strategy, and ensure our DFT solutions are properly verified for all usage scenarios.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Job duties and responsibilities:

Deliver confidence in the correctness of the design for testability and debug features of the server scale CPU SoC.
Integrate DFT verification into the overall ASIC design flow.
Prepare silicon debug verification strategy, test plan, and readiness for tester.
Participate in post-manufacturing silicon bring-up tasks.

Minimum qualifications:

Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
3 years of experience with DFT features (e.g., JTAG/MBIST) or functional infrastructure/global validation experience.
Experience with verification methods (e.g. UVM), and experience with a scripting language (e.g., Python, Perl, TCL).
Experience with SystemVerilog coding for design and verification, SoC development cycle.