Design Verification Engineer | Google Job | Bangalore, KA

Job description:

Google is conducting an interview for the post of Design Verification Engineer.

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a part of the Google Silicon Platform IP team, you will work on the verification of Google’s SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the interconnect, memory subsystem, power management blocks, and SOC pervasive IP. You will also work on developing high performance VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs. Our approach to building SOCs is based on scalability. Your work will be verifying generalized subsystems, and developing the associated methodologies and tools needed to solve the problem.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Job duties and responsibilities:

  • Plan and execute the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Develop cross-language tools and scalable verification methodologies.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks, close coverage measures to identify verification holes, and show progress towards tape-out.

Qualifications and experience required:

  • Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience
  • 2 years of experience working with digital logic at RTL level using System Verilog or C/C++

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering or Computer Science
  • Experience with Interconnect Protocols (e.g., ACE, CHI, CCIX, CXL)
  • Experience with building verification methodologies that span simulation, emulation, and FPGA prototypes
  • Architectural background in one or more of: Operating Systems, Memory Management, Caches Hierarchies, Coherency

Job/Req. ID: N/A

Company: Google

Location: Bangalore, KA

Job Category: VLSI or Computer Science or Electrical Engineering

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