Job description:
Google is hiring for the post of RTL Design Engineer.
Job duties and responsibilities:
In this role, you will have to collaborate with the central DFT team to model essential DFT features, required for the integration of custom cells and memories into the SoC. You will gain the opportunity to work with a team and gain insights into the design trade-offs made to optimize the Power, Performance, and Area (PPA) of SoCs.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
- Develop Verilog models for custom standard cells and memories, and collaborate with the DFT team to model essential DFT features.
- Work with the design team to comprehend design trade-offs and participate in the design and implementation of custom cells and memories.
- Verify the functionality of custom cells and memories diligently.
- Document the design and implementation of custom cells and memories.
Minimum qualifications:
- Bachelor’s degree in Computer Engineering, Electrical Engineering, a related field, or equivalent practical experience.
- 4 years of experience with Verilog language.
- Experience in Complementary Metal Oxide Semiconductor (CMOS) Digital Circuits and Memories.
Preferred qualifications:
- Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
- 4 years of experience in developing Verilog models for cells or memories.
- Experience using tools to validate Verilog models.
- Knowledge of Design for Test (DFT) features like BIST and SCAN.
- Excellent analytical, problem-solving, communication, and teamwork skills.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job category: VLSI Engineering
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