Job description:
The NVIDIA System-On-Chip (SOC) group is looking for a star candidate with an interest in SOC level front-end design for distributed SOC IPs. Along with RTL design knowledge, you must have a real passion for methodologies and automation solutions that enable the implementation in the most optimized and scalable way.
In this position, you will get the chance to work on complex Tegra and GPU chips while interfacing directly with System Architecture, unit-level ASIC, Physical Design, DFT and other teams. Additionally, you will be involved in defining and creating methodologies that create more efficient and flexible SOCs in future.
Job duties and responsibilities:
- Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
- Execute on the RTL implementation and delivery for distributed SOC IPs across the project cycle.
- Responsible for front-end design quality checks, synthesis, reviews and driving those with cross-functional teams.
Qualifications and Experience required:
- B.Tech or M.Tech or equivalent experience in Electronics or Computer Engineering.
- 2+ years of industry experience in chip design, with exposure to RTL design and design automation. Knowledge of SOC Debug related IPs is a plus.
- Excellent analytical and problem-solving skills.
- Experience in RTL design (Verilog), System-On-Chip design/implementation flow, and design automation.
- Strong coding skills in Perl, Python, or other industry-standard scripting languages.
- Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.
- Excellent communication skills to interact with cross functional teams to build consensus.
- Good teamwork spirit and collaboration skills with team members.
- Experience in synthesis, physical design and DFT s a plus.
Job/Req. ID: JR1950660
Company: NVIDIA
Location: Bengaluru, KA
Job Category: VLSI Engineering
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