CPU/DSP DV Engineer | Cadence | Pune, MH

Job description:

Cadence is conducting an interview for the post of CPU/DSP DV Engineer.

Job duties and responsibilities:

  • As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals.
  • You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • You will also assist with developing testplans, debugging failures and analyzing coverage information.
  • You will work closely with the RTL and EDA teams.

Qualifications, Required Skills and Experience:

  • BS (or higher) in EE/Computer Engineering
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
  • Knowledge of SystemVerilog and UVM methodology
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Experience with assembly language programming is a plus
  • Excellent written and oral communication skills
  • Candidate must be self-motivated and capable of working independently or as part of a team
  • Knowledge of Formal Verification will be a plus

Job/Req. ID: R36704


LocationPune, MH

Job CategoryVLSI Engineering

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