Engineer I – Validation | Microchip Technology | CA – San Jose – 3850 N. First St

November 30, 2022

Job description:

Microchip Technology is conducting an interview for the post of Validation Engineer I.

Microchip has been consistently recognized as one of the best places to work by prestigious publications like Forbes, Bay Area News and Phoenix Business Journal. The FPGA Business Unit (formerly Actel, with a 35+ year uninterrupted legacy of providing programmable logic solutions) is one of the largest and most profitable BUs inside Microchip. We have revolutionized the FPGA industry with the industry’s most awarded FPGA families – the PolarFire FPGA family and the first RISC-V based PolarFire SoC, delivering class leading power efficiency, reliability and security. With this portfolio, we have enabled commercial applications like the world’s most innovative AI-enabled embedded vision and smart automation products, the world’s most secure and reliable 5G communications networks, as well as the world’s most sophisticated aerospace products that have delivered payloads to Mars and beyond. If you are looking to be a part of a team that is transforming the world of low power compute whilst delivering exceptional top line growth rates, you will be challenged to find a better place to contribute, grow your career and learn to deliver truly remarkable solutions.

The Candidate will be able to use FPGAs to create systems level designs to bring up and debug use models in the lab.
Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
Develop high level system and product level validation plans for new and existing silicon products and projects, execute per plan. Review dependencies, estimate effort and identify and communicate risk.
Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
Be an effective contributor in a cross-functional team-oriented environment.
Write high quality code in Verilog, VHDL and C code. Maintain existing code.
Support regression and re-use.
Learn new system designs and validation methodologies.
Understand FPGA architectures.
Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.
Define and improve processes followed in the department; follow quality metrics and assess per project.
Must be willing to take late night or early morning calls to interface with engineers working in India Standard Time zone, when and if required.

Requirements/Qualifications:

Minimum Qualifications:

BS EE/CE with 0 to 2 years of experience.
Knowledge of FPGA architectures is a must.
Possess an understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios.
Design with RTL coding in Verilog or VHDL is a must.
Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools.
Technical background in FPGA prototype emulation, and debug.
Technical background in silicon validation, failure analysis and debug.
Demonstrate board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, FPGA integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chip scope, Altera Signalscope, Lattice Reveal).
Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
Strong commitment to quality and customer satisfaction.
Excellent verbal and written communication skills.
Able to travel 0-2 times annually if required.

Preferred qualifications:

C, C++ or object-oriented programming skills is desirable.
Knowledge of Linux is desirable.
Knowledge of U-Boot is desirable.
Knowledge and experience in embedded firmware development and debug is desirable.
Knowledge of RISC-V architecture and Instruction Set is desirable.
Knowledge of PERL/TCL/python scripting is desirable.
Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable.
Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA is a big plus:
- PCIe Gen3/4/5
- Ethernet 1/10/25/40/100/200G
- Interlaken (4.25 to 412.5 Gbps)
- OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
- (E,X,XGS,NG)-PON or 100G-EPON
- Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
- JESD204C (6.375 to 32 Gbps)
Design and debug experience for any of the below high-speed serial communications protocols is a plus:
- Hybrid Memory Cube
- CPRI Rate 1 to 10+
- Serial Rapid IO 4.1
- Firewire
- Litefast
- USB 3.0
- SATA I, II, III
- Fiber Channel
- CoaXpress