ASIC Physical Design and Implementation Engineer | Google | Bangalore, KA

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Job description:

Google is conducting an interview for the post of ASIC Physical Design and Implementation Engineer.

About the job:

Google’s computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As an ASIC Physical Design and Implementation Engineer, you will develop high performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will work with Architects and Logic Designers to drive architectural feasibility studies, develop timing, power, and area design goals, and explore Register Transfer Language (RTL)/design trade-offs for physical design closure. You’ll also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Google’s team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Job duties and responsibilities:

  • Develop all aspects of ASIC RTL to GDS (Graphic Data Stream) implementation for high
  • Power Performance Area (PPA) designs.
  • Manage block and full-chip level physical implementation and Quality of Results (QoR), including timing and area.

Qualifications and experience required:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • 2 years of experience in Physical Design.
  • Experience in high performance synthesis, PnR, and sign-off optimizations. Experience in sign-off convergence, including STA, electrical checks, and physical verification.
  • Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).

Preferred qualifications:

  • Experience in computer architecture.
  • Knowledge of Verilog/SystemVerilog.
  • Understanding of circuit design, device physics, and deep submicron technology.
  • Excellent scripting skills with Python, Tcl, and/or Perl.

Job/Req. ID: N/A

Company: Google

LocationBangalore, KA

Job CategoryVLSI or Electrical Engineering

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