Top and Latest Laptops and Computer Accessories, check out now
Job description:
Cadence is conducting an interview for the post of Design Engineer II.
Job duties and responsibilities:
- As a member of the Design Team for Xtensa processors you will be responsible for RTL design of blocks in the microprocessor cores and their peripherals.
- Under the mentor-ship of a RTL designer, you will create microarchitecture of the design and implement RTL code,
- You will carry out simulation, write assertion checks to meet target design goals.
- You will be responsible for making sure your designed block is free of any lint issues
- You will be responsible for timing closure of your design
- You will also assist with developing test plans, debugging failures and analyzing coverage information.
- You will work closely with the Verification and EDA teams
Requirement:
- Knowledge of computer architecture
- Digital logic design and verification fundamentals
- Knowledge of Verilog and exposure to scripting languages like Perl, Unix shell or similar languages
- Some experience with assembly language programming required
Job/Req. ID: R41968
Company: Cadence
Location: Pune, MH
Job Category: VLSI Engineering
Join all India VLSI Jobs Telegram Group
Important note: This job is 30+ days old, and is still active
