Graduate Intern Technical – Layout | Intel | Bangalore, KA

Job description:

Intel is conducting an internship for Engineers.

Job duties and responsibilities:

In this position you will be involving in the training design and development of next generation Server SOCsCPUs

Your responsibilities will include some of the following but not limited to:

  • Assist design unit owner in Register Transfer Level RTL modeling amp functional validation
  • Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next generation deep submicron embedded circuit solutions
  • Verify the circuit behavior against the original simulation model and first silicon Define VLSI Structural Design methodology and developing design flows
  • Implement structural physical designs such as synthesis floor planning powergrid and clock tree designs timing budgeting and closure place and route RCextraction and integration
  • Verify structural physical designs such as functional equivalency timingperformance noise layout design rules reliability and power

Qualifications required:

You should be a student Post graduate

Masters ME/MTech/MS currently pursuing studies in relevant field with good understanding of semiconductor physics and basic PC computer architecture

Additional qualifications include:

  • Familiarity with Very Large Scale Integration VLSI Complementary MetalOxide Semiconductor CMOS logic circuit design
  • Well versed in UNIX C programming and relevant Computer Aided Design CAD tools

Inside this Business Group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC’s and critical IP’s sustain Intels Xeon and 5G networking roadmap.

Job/Req. ID: JR0240658

Company: Intel

Location: Bangalore, KA

Job CategoryVLSI Engineering

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