SoC DFT Engineer, Google Cloud | Google | Bangalore, KA

Job description:

Google is conducting an interview for the post of SoC DFT Engineer.

Job duties and responsibilities

  • Own DFT logic, Pre-silicon verification, and work with test engineers post silicon. Develop DFT strategy and architecture.
  • Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), TAP controller, Clock Control block, and other DFT IP blocks.
  • Insert and hook up Memory Built-In Self Test (MBIST) logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
  • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Minimum qualifications:

  • 3 years of experience in DFT using electronic design automation (EDA) test tools.
  • Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
  • Experience with ASIC DFT synthesis, simulation, and verification flow.
  • Experience in DFT specification definition architecture and insertion.

Preferred qualifications:

  • Master’s degree in Electrical Engineering. Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
  • Experience in SoC cycles, silicon bring-up, and silicon debug activities.
  • Experience in fault modeling.

Job/Req. ID: N/A

Company: Google

LocationBangalore, KA

Job category: Electrical or VLSI Engineering

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