googleJob description:
Google Custom IP (Foundry Tech) team seeks a mid-level design engineer with expertise in the timing characterization of custom digital Complementary Metal-Oxide-Semiconductor (CMOS) circuits.
Job duties and responsibilities:
- Generate timing collaterals for custom digital CMOS circuits utilizing industry-standard tools such as Liberate or Silicon-Spice. Analyze and validate characterized timing data.
- Perform statistical simulations to ensure the robustness of custom circuits.
- Participate in Silicon-Spice correlation activities to improve Performance, Power, Area (PPA) of custom digital circuits.
- Collaborate closely with the internal circuit design team and the System-on-a-Chip (SoC) team and understand customization requirements.
- Provide guidance and mentorship to junior and temporary engineers, as necessary.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in characterizing standard-cells or memory.
- Experience in writing spice decks and basics of CMOS circuits.
Preferred qualifications:
- Master’s degree in VLSI Integration, Computer Engineering, Electronics Engineering, or a related field.
- Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido.
- Experience with characterization tools (e.g., SiliconSmart, Liberate).
- Experience in PERL/Shell/TCL scripting or similar languages, with the ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages.
- Understanding of CMOS circuits and timing concepts (e.g., setup, hold).
- Understanding of Liberty Variation Format (LVF) and Composite Current Source (CCS) models.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: VLSI Engineering
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