Standard Cell Design Graduate Intern | Intel Job | Bangalore, KA

April 12, 2024

Job description:

Intel is hiring for the post of Standard Cell Design Graduate Intern.

Job duties and responsibilities:

Responsibilities for this position may encompass a wide range of technical tasks. The U.S. experience and educational requirements will vary significantly depending on the specific needs of the job. Assignments typically occur during the summer or short periods during school breaks.

Qualifications required:

Minimum qualifications are necessary to be initially considered for this position. Preferred qualifications are additional criteria and are considered advantageous in identifying top candidates.

Minimum qualifications:

Candidates must be pursuing a Master’s degree in electronics engineering, hardware engineering, electrical engineering, computer science/engineering, or related fields with knowledge in:

Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
Strong understanding of device physics.
Proficient in Python programming and automation with several years of experience in VLSI Design Automation areas (such as Physical Design Automation, Simulation, Timing Analysis, Reliability Analysis).
Excellent collaboration skills across geographically distributed teams, with the ability to handle ambiguity while developing expertise in new areas and delivering quantifiable results.
Excellent written and verbal communication skills, with a strong customer/result orientation and the ability to work flexibly with external and internal partners, as well as EDA vendors.

Preferred qualifications:

Experience with industry-standard ASIC tools like Design Compiler, Genus, Tempus, ICV.
Experience in digital circuit design, front-end model creation, and functional verification.
Familiarity with standard cell library characterization, liberty models, and cross-validations with front-end models and liberty models.
Experience collaborating with EDA vendors to enhance features and capabilities.
Knowledge of industry-standard EDA tools for VLSI circuit and layout design.
Familiarity with the Linux environment and its development tools.
Experience in standard cell-level PPA modeling, simulation, and ROI analysis.
Proficiency in CMOS power modeling and cell-level optimization.
Understanding of CMOS and standard cell-level device variation and Aging analysis.
Strong engineering acumen and analytical skills, with excellent debugging capabilities.
Customer-oriented and adaptable to dynamic environments.