Job description:
Qualcomm is conducting an interview for the post of Digital ASIC Design Engineer.
Job duties and responsibilities:
- Understanding the RTL design of IPs and supporting them in integration across different sub-systems
- RTL Design validation in terms of
- Clock Domain Crossing (CDC) check
- Synthesis and Static Timing Analysis
- Formal and functional verification
- Lint check of RTL
- Power domain crossing checks
- Power aware simulation
- Design for Testability (DFT) checks
- Close collaboration with different teams across various time zones.
Qualifications and experience required:
Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Skillset/experience:
- Strong knowledge in digital logic design (Data path and Finite Sate Machine (FSM) Design).
- Experience in RTL Design and Verilog or System Verilog coding
- Familiarity with front-end design flows (synthesis, formal verification, static timing analysis, CDC) is a plus
- Scripting in Perl/Python/Shell/Tcl for productivity is a plus
Minimum Qualifications:
- Bachelor’s degree in Science, Engineering, or related field
- 2-6 years of experience in Digital ASIC design.
Job/Req. ID: 3050593
Company: Qualcomm
Location: Hyderabad, Telangana
Job Category: VLSI Engineering
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