Job description:
AMD is conducting an interview for the post of Silicon Design Engineer.
Job duties and responsibilities:
As the part of the Programmable Clock & Methodologies team in India for AMD’s Adaptive-Embedded Computing products, you will be responsible for design and development of clocking solutions that meet the high standards of AMD’s AECG products. This will involve working a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office.
An integral part of AMD’s programmable logic group, the global Clock team is tasked with implementing the programmable clock and Methodologies of AMD’s growing range of Adaptive-Embedded Computing products. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system, functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional architecture, other Programable Logic groups, integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology.
The Person:
The type of person who will be successful in this role is highly inquisitive and a team player who communicates proactively. They will exhibit excellent written and verbal communication skills and will be highly analytical. The candidate should enjoy collaborating with engineers with diverse skillsets and bringing their expertise to bear on solving challenging Programable logic problems. The successful candidate will have comprehensive knowledge of ASIC design methodology.
Job duties and responsibilities:
- Investigate Clock architectures and circuits solution, Determine creative design approaches and parameters.
- Implement FPGA IP in physical design flow using ICC2, STA.
- Support RTL functional simulation and verification
- Provide physical implementation design support using STA, EM, IR, Power analysis tools.
- Develop SDC constraint and do timing analysis using Prime Time or equivalent timing analysis tool.
- Run static checks using LINT, LEC, CDC
- Implement IP in FPGA environment using Vivado or similar tools/flows.
- Improve the efficiency and quality using scripting and programming.
- Support Silicon testing on bench or ATE tester.
Preferred experience:
- Strong VLSI Fundamentals, Digital Systems & Circuits design, deep submicron CMOS design based on FinFETs technology.
- Comprehensive knowledge of ASIC design methodology.
- Physical Design Tools: RTL to GDSII, ICC2, PnR, CTS, Star RC, STA.
- Circuit Design Tools: Cadence (Virtuoso – Schematics and Layout), ADE-XL, Spectre.
- Verilog, Perl/Python/C++ scripting and programming.
- HSPICE, Wave Viewer, ModelSim.
- Prior work experience in FPGA design using VIVADO tool and silicon testing is a plus.
Qualifications and experience required:
Bachelors or Masters degree in Electronics or Electrical Engineering/computer engineering with 2+Years of experience.
Job/Req. ID: 22269
Company: AMD
Location: Hyderabad, Telangana
Job Category: Electrical or Electronics or Computer Engineering
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