Job description:
Cadence is conducting an interview for the post of Formal Verification Engineer.
Requirements:
- BE/BTech/ME/MTech – Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- Strong background on verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on System Verilog Assertion coding experience and Formal verification environment development is required.
- Exposure to cadence Jasper tool with apps like FPV, UNR, COV, CSR, C2RTL desirable.
- Team player with strong communication skills, and ability to work independently on the verification of a portion of the design.
- Prior experience in IP development teams would be an added advantage.
Job/Req. ID: R43704
Company: Cadence
Location: Bangalore
Job Category: VLSI Engineering
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