Analog Layout Design Engineer Job Opportunity | Intel Jobs | Bangalore, KA

Job description:

Intel is hiring for the post of Analog Layout Design Engineers.

Job duties and responsibilities:

  • Design complex layouts of analog signal circuits based on given design specifications and conduct comprehensive design verification using various tools to ensure compliance with process design rules, electron migration, voltage drop (IR), ESD, and other reliability criteria.
  • Analyze floorplans, power grids, ESD, bumps, and conduct thorough verification on analog blocks. Perform microfloor planning and detailed signal planning for intricate analog circuits to meet performance and electrical requirements, such as shielding and matching, optimizing for area, power, RV, and performance.
  • Develop and implement innovative analog layout methodologies to enhance layout productivity and quality.
  • Collaborate with analog circuit design, process technology, and package design teams to meet design specifications, plan work, and address layout tradeoffs as necessary.
  • Troubleshoot a wide range of issues related to analog layout design, including design and tool/flow/methodology challenges.

Qualifications and experience required:

  • 2 years of experience in analog layout.
  • M.Tech in VLSI Design / B.Tech in Electronics and Communication Engineering.

Additional qualifications:

  • Proficient knowledge of CMOS device physics.
  • Understanding of basic circuit and layout blocks in deep sub-micron CMOS/FinFET technology.
  • Exposure to basic analog layout blocks in Cadence Virtuoso tool environment; exposure to Synopsys Custom Compiler tool environment is a plus.

Job/Req. ID: JR0261696

Company: Intel

LocationBangalore, KA

Job CategoryVLSI Engineering

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