Synopsys is conducting an internship for Engineers.
Job duties and responsibilities:
Responsible for developing backend ASIC design from netlist to gdsii & Physical verification for Testchip blocks. Also need to work on automation using perl and tcl for enhancing the flows .
Qualifications and Experience required:
- Bachelors or Masters degree in electronics or electrical engineering (B.Tech/M. Tech) or equivalent from reputed universities.
- Knowledge on VLSI technology
- Gate level and circuit level understanding of CMOS logic design.
- Experience in physical design implementation flow (floorplan, placement, CTS and routing)
- Scripting in Perl and TCL
- Understanding of timing and design closure aspects
- DRC/LVS understanding
- Good communication, interpersonal skills and team player
Job/Req. ID: 34483BR
Location: Hyderabad, Telangana
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